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general description the MAX8753 quadruple-output dc-dc converter pro- vides the regulated voltages required by active-matrix, thin-film transistor (tft), liquid-crystal displays (lcds). it includes a high-power step-up regulator (v main ), two low-power charge pumps (v pos and v neg ), and a low- voltage 300ma linear regulator (v logic ). the step-up dc-dc converter is a high-frequency (1mhz) current-mode regulator with a built-in power mosfet that allows the use of ultra-small inductors and ceramic capacitors. it provides fast transient response to pulsed loads and includes an automatic pulse-skip- ping mode that increases efficiency over a wide-load current range. the 1.5a current limit allows a +10v out- put at more than 300ma from a +3.3v input. the two charge pumps independently regulate one positive and one negative output voltage. the positive charge pump is a voltage tripler that accepts an input voltage up to +13v and delivers a 20ma output up to +28v without external switches or diodes. the negative charge pump inverts an input voltage up to +24v and delivers a 20ma negative output using external diodes. the logic linear regulator converts the ic? +2.6v-to- +5.5v input to a regulated +2.5v or adjustable output. the MAX8753 is available in a 28-pin thin qfn pack- age with a maximum thickness of 0.8mm for ultra-thin lcd panel design. applications notebook computers, pdas car navigation displays lcd monitors features 3 integrated dc-dc converters, 1 ldo 1mhz current-mode pwm boost regulator up to +13v main high-power output ?% accuracy high efficiency (90%) dual charge-pump outputs no external diodes for positive charge pump up to +28v positive charge-pump output negative charge-pump output 300ma logic linear regulator +2.6v to +5.5v input operating range 0.8ma quiescent current internal supply sequencing and soft-start thermal protection ultra-thin, 28-pin tqfn package (0.8mm max) MAX8753 tft lcd dc-dc converter with integrated charge pumps ________________________________________________________________ maxim integrated products 1 19-3919; rev 0; 1/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information MAX8753 in supp supn shdn lcdon outl fbl dlp intg lx pgnd gnd fb c3p fbn ref outp fbp c1n c1p c2n c2p v in +2.6v to +5.5v v main v main v neg v pos v logic minimal operating circuit part temp range pin-package MAX8753eti+ -40 c to 85 c 28 thin qfn (5mm x 5mm) pin configuration MAX8753 tqfn top view 26 27 25 24 10 9 11 n.c. c2p outp intg fb 12 supp n.c. c3p i.c. lx i.c. fbn 12 shdn 4567 20 21 19 17 16 15 lcdon c1n n.c. in outl fbl c2n supn 3 18 28 8 c1p fbp dlp 23 13 gnd n.c. 22 14 ref pgnd + denotes lead-free package.
MAX8753 tft lcd dc-dc converter with integrated charge pumps 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, shdn , lcdon to gnd ......................................-0.3v to +6v dlp, outl, fbl, fbp, fbn, intg, fb, ref to gnd ............................................-0.3v to (v in + 0.3v) pgnd to gnd .......................................................-0.3v to +0.3v lx to pgnd ............................................................-0.3v to +14v supp to pgnd .......................................................-0.3v to +14v c1n, c2n to pgnd ................................-0.3v to (v supp + 0.3v) outp to pgnd ........................................(v supp - 0.3v) to +30v c1p to c1n, c2p to c2n, outp to c2p ................-0.3v to +14v supn to pgnd.......................................................-0.3v to +30v c3p to pgnd.........................................-0.3v to (v supn + 0.3v) continuous power dissipation (t a = +70 c) 28-pin 5mm x 5mm tqfn (derated 21.3mw/ c above +70 c)............................................................1702mw operating temperature range .......................... -40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (circuit of figure 1, v in = 3.0v, shdn = lcdon = in, v supp = v supn = 10v, pgnd = gnd, c ref = 0.22f, c intg = 470pf, t a = 0? to +85? . typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units input supplies input supply range v in 2.6 5.5 v input undervoltage threshold v uvlo v in rising, 100mv hysteresis (typ) 2.1 2.3 2.5 v in quiescent supply current i in v fb = v fbp = 1.5v, v fbn = -0.2v 0.8 1.5 ma in shutdown current v shdn = 0, v in = 5v 0.1 10 a supp supply range v supp 713v supp quiescent current i supp v fbp = 1.5v 0.4 0.8 ma supp shutdown current v shdn = 0, v supp = 14v, outp floating 0.1 10 a supn supply range v supn 724v supn quiescent current i supn v fbn = -0.2v 0.4 0.8 ma supn shutdown current v shdn = 0, v supn = 24v 0.1 10 a main boost converter output voltage range v main v in 13 v fb regulation voltage v fb 1.232 1.245 1.258 v fb input bias current i fb v fb = 1.25v, intg = gnd 125 275 na fb undervoltage shutdown threshold fb falling 75 125 200 mv operating frequency f osc 0.85 1.00 1.15 mhz oscillator maximum duty cycle 78 85 90 % load regulation i main = 0 to 100ma, v main = 10v 0.2 % line regulation 0.1 %/v intg transconductance 320 s lx switch on-resistance r lx ( on ) i lx = 100ma 0.35 0.7 ? lx leakage current i lx v lx = 13v, v shdn = 0 0.01 20 a
MAX8753 tft lcd dc-dc converter with integrated charge pumps _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = 3.0v, shdn = lcdon = in, v supp = v supn = 10v, pgnd = gnd, c ref = 0.22f, c intg = 470pf, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units phase i = soft-start (1.0ms) 0.38 phase ii = soft-start (1.0ms) 0.75 phase iii = soft-start (1.0ms) 1.13 lx current limit i lx ( max ) phase iv = fully on (> 3.0ms) 1.08 1.45 1.80 a soft-start period t ss power-up to the end of phase iii 3072 / f osc s positive charge pump v supp input supply range v supp 713v v supp overvoltage threshold v supp = rising, hysteresis (typ) = 200mv 13.2 13.6 14.0 v outp operating range v supp 28 v operating frequency 0.25 x f osc hz fbp regulation voltage v fbp 1.213 1.250 1.287 v fbp line regulation v supp = 8v to 12v, v outp = 20v, i outp = 5ma 10 mv fbp input bias current i fbp v fbp = 1.5v -50 +50 na soft-start period v ssp 1024 / f osc s c1n, c2n high-side on- resistance i source = 50ma 15 ? c1n, c2n low-side on- resistance i sink = 50ma 5 ? c1p switch on-resistance i source = 50ma 8 ? c2p switch on-resistance i source = 50ma 8 ? outp switch on-resistance i source = 50ma 8 ? negative charge pump v supn input supply range v supn 724v operating frequency 0.25 x f osc hz fbn regulation voltage v fbn 213 250 287 mv fbn line regulation v supn = 8v to 24v, v outn = -10v, i outn = 5ma 10 mv fbn input bias current i fbn v fbn = -0.05v -50 +50 na soft-start period v ssn 1024 / fosc s c3p high-side on-resistance i sink = 50ma 15 ? c3p low-side on-resistance i sink = 50ma 10 ?
MAX8753 tft lcd dc-dc converter with integrated charge pumps 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 3.0v, shdn = lcdon = in, v supp = v supn = 10v, pgnd = gnd, c ref = 0.22f, c intg = 470pf, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units v logic regulator fbl regulation voltage v fbl i outl = 0 to 300ma 1.225 1.250 1.275 v fbl input bias current i fbl v fbl = 1.3v -50 +50 na fbl undervoltage lockout v fbl_uv v fbl rising, hysteresis (typ) = 125mv 1.100 1.125 1.150 v fbl dual-mode threshold v fbl = rising 220 250 280 mv outl voltage accuracy (preset mode) v fbl = gnd, i outl = 0 to 300ma 2.425 2.500 2.575 v outl load regulation i outl = 0 to 300ma -2 % outl line regulation v in = 2.6v to 5.5v 0.1 % outl on-resistance v in = 3.3v, i outl = 100ma 0.7 1.5 ? outl short-circuit current v outl = gnd, v fbl = 1v 500 ma reference reference voltage v ref -2a < i ref < +50a 1.231 1.250 1.269 v reference undervoltage threshold v ref rising 0.9 1.05 1.2 v logic signals lcdon, shdn input low voltage hysteresis = 0.15 x v in (typ) 0.9 v lcdon, shdn input high voltage 2.1 v shdn input current i shdn v shdn = 0 to in 0.01 1a lcdon input current i lcdon v lcdon = 0 to in 0.01 1a sequencing dlp capacitor charge current v dlp = 0.5v 4 5 6 a dlp turn-on threshold v dlp = rising 1.20 1.25 1.30 v dlp discharge switch on-resistance v shdn = 0 40 ? fault protection duration to trigger fault t fault 50 ms fbl fault-trip level falling edge 0.95 1.01 1.08 v fb, fbp fault-trip level falling edge 1.07 1.10 1.14 v fbn fault-trip level rising edge 450 500 550 mv thermal-shutdown threshold typical hysteresis = 15 c +160 c dual-mode is a trademark of maxim integrated products, inc.
MAX8753 tft lcd dc-dc converter with integrated charge pumps _______________________________________________________________________________________ 5 electrical characteristics (circuit of figure 1, v in = 3.0v, shdn = lcdon = in, v supp = v supn = 10v, pgnd = gnd, c ref = 0.22f, c intg = 470pf, t a = -40 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units input supplies input supply range v in 2.6 5.5 v input undervoltage threshold v uvlo v in rising, 100mv hysteresis (typ) 2.1 2.5 v in quiescent supply current i in v fb = v fbp = 1.5v, v fbn = -0.2v 1.5 ma supp supply range v supp 713v supp quiescent current i supp v fbp = 1.5v 0.8 ma supn supply range v supn 724v supn quiescent current i supn v fbn = -0.2v 0.8 ma main boost converter output voltage range v main v in 13 v fb regulation voltage v fb 1.225 1.258 v fb undervoltage shutdown threshold fb falling 75 200 mv operating frequency f osc 0.75 1.25 mhz lx switch on-resistance r lx ( on ) i lx = 100ma 0.7 ? lx current limit i lx ( max ) phase iv = fully on (> 3.0ms) 1.08 1.8 a positive charge pump v supp input supply range v supp 713v v supp overvoltage threshold v supp = rising, hysteresis (typ) = 200mv 13.2 14.0 v fbp regulation voltage v fbp 1.213 1.287 v negative charge pump v supn input supply range v supn 724v fbn regulation voltage v fbn 213 287 mv v logic regulator fbl regulation voltage v fbl i outl = 0 to 300ma 1.220 1.275 v outl on-resistance v in = 3.3v, i outl = 100ma 1.5 ? reference reference voltage v ref -2a < i ref < +50a 1.225 1.269 v reference undervoltage threshold v ref rising 0.9 1.2 v logic signals lcdon, shdn input low voltage hysteresis = 0.15 x v in (typ) 0.9 v lcdon, shdn input high voltage 2.1 v
MAX8753 tft lcd dc-dc converter with integrated charge pumps 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 3.0v, shdn = lcdon = in, v supp = v supn = 10v, pgnd = gnd, c ref = 0.22f, c intg = 470pf, t a = -40 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units sequencing dlp turn-on threshold v dlp = rising 1.2 1.3 v fbl fault-trip level falling edge 0.95 1.08 v fb, fbl, fbp fault-trip level falling edge 1.07 1.14 v note 1: specifications to -40 c are guaranteed by design, not production tested. 50 60 80 70 90 100 step-up efficiency vs. load current MAX8753toc01 load current (ma) efficiency (%) 0100 50 150 200 v in = 3.0v v in = 5.0v normalized v main vs. load current load current (ma) 8.94 8.96 9.02 9.00 8.98 9.04 9.06 MAX8753toc02 v main (v) 0 300 100 500 200 400 600 v in = 3.0v v in = 5.0v 200 300 500 400 600 700 step-up maximum output current vs. input voltage MAX8753toc03 input voltage (v) i main (ma) 24 35 6 2.47 2.48 2.50 2.49 2.51 2.52 normalized outl voltage vs. outl load current MAX8753toc04 outl load current (ma) v outl (v) 0 150 200 100 50 250 300 v in = 3.0v v in = 5.0v 0 0.10 0.05 0.25 0.20 0.15 0.30 0.35 0.40 outl dropout voltage vs. outl load current MAX8753toc05 outl load current (ma) v in - v logic (v) 0 150 200 100 50 250 300 -11.4 -11.2 -10.8 -11.0 -10.6 -10.4 outn voltage vs. outn load current MAX8753toc06 outn load current (ma) v outn (v) 010 515 20 v supn = 9v v supn = 10v typical operating characteristics (circuit of figure 1, v in = 3v, v main = 9v, t a = +25 c, unless otherwise noted.)
MAX8753 tft lcd dc-dc converter with integrated charge pumps _______________________________________________________________________________________ 7 24.2 24.1 24.0 23.9 23.8 010 51520 outp voltage vs. outp load current MAX8753toc07 outp load current (ma) v outp (v) v supp = 9v v supp = 10v 1.20 1.10 1.00 1.15 1.05 0.95 0.90 2.5 3.0 4.0 3.5 4.5 5.0 5.5 switching frequency vs. input voltage MAX8753toc08 input voltage (v) switching frequency (mhz) i main = 100ma 1.248 1.249 1.250 1.251 1.252 reference voltage vs. reference current MAX8753toc09 reference current ( a) reference voltage (v) 030 20 10 40 50 v main transient response MAX8753toc10 0 0 9v a c b 40 s/div a. load fet gate, 5v/div c. i lx , 500ma/div b. v main , 200mv/div i main = 20ma to 160ma v main 3-pulse transient response MAX8753toc11 0 0 9v b c a 10 s/div a. load fet gate, 5v/div c. i lx , 500ma/div b. v main , 200mv/div i main = 20ma to 1a, 2 s pulse v main switching waveforms MAX8753toc12 9v 0 0 b c a 400ns/div a. v lx , 5v/div c. v main , 50mv/div b. i lx , 500ma/div i main = 160ma v main soft-start MAX8753toc13 0 0 0 b c a 1ms/div a. shdn, 5v/div c. i lx , 500ma/div b. v main , 5v/div i main = 160ma outn startup v main soft-start (no load) MAX8753toc14 0 0 0 b c a 1ms/div a. shdn, 5v/div c. i lx , 500ma/div b. v main , 5v/div outn startup v main startup outp soft-start MAX8753toc15 0 0 b a 400 s/div a. outp, 10v/div i outp = 20ma b. i supp , 500ma/div typical operating characteristics (continued) (circuit of figure 1, v in = 3v, v main = 9v, t a = +25 c, unless otherwise noted.)
MAX8753 tft lcd dc-dc converter with integrated charge pumps 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 3v, v main = 9v, t a = +25 c, unless otherwise noted.) outp switching waveforms MAX8753toc16 24v 0 0 a c b 4 s/div a. v cin , 5v/div c. v outp , 200mv/div b. v c2n , 5v/div i outp = 20ma outn soft-start MAX8753toc17 0 0 0 a c b 1ms/div a. shdn, 5v/div c. i supn , 200ma/div b. outn, 5v/div i outn = 20ma outn switching waveforms MAX8753toc18 -11v 0 a b 10 s/div a. v c3p , 5v/div i outn = 10ma b. v outn , 100mv/div outl soft-start MAX8753toc19 0 0 0 a c b 400 s/div a. shdn, 5v/div c. v ref , 1v/div b. outl, 1v/div r outl = 10 ? outl transient response MAX8753toc20 0 2.5v a b 100 s/div a. v outl , 50v/div i outl = 10ma to 300ma b. i outl , 100ma/div power-up sequencing MAX8753toc21 0 0 9v 0 24v 0 b c a f e d 4ms/div a. shdn, 5v/div d. v outn , 10v/div b. v outl , 5v/div e. v outp , 10v/div c. v main , 10v/div f. v dlp , 2v/div power-down sequencing MAX8753toc22 0 0 9v -11v 24v 0 b c a f e d 4ms/div a. shdn, 5v/div d. v outn , 10v/div b. v outl , 5v/div e. v outp , 10v/div c. v main , 10v/div f. v ref , 1v/div fault timer MAX8753toc23 2.5v 24v -11v 0 9v b c a e d 10ms/div a. v main , 5v/div d. v lx , 10v/div b. v outp , 20v/div e. v outl , 2v/div c. v outn , 10v/div r main = open to 18 ?
MAX8753 tft lcd dc-dc converter with integrated charge pumps _______________________________________________________________________________________ 9 pin description pin name function 1 supp positive charge-pump supply voltage. bypass to pgnd with a 0.1f capacitor. 2, 12, 20, 23 n.c. no connection. not internally connected. 3 c2n negative terminal of flying capacitor c2 4 c2p positive terminal of flying capacitor c2 5 outp positive charge-pump output 6 intg step-up regulator integrator output. connect a 470pf capacitor from intg to gnd. 7fb step-up converter feedback input. regulates to 1.245v (nominal). connect a resistor-divider from the output (v main ) to fb to analog ground (gnd). place the resistor-divider within 5mm of fb. 8 fbp positive charge-pump feedback input. regulates to 1.25v (nominal). connect a resistor-divider from the output (outp) to fbp to analog ground (gnd). place the resistor-divider within 5mm of fbp. 9 fbl logic linear regulator dual-mode feedback input. connect fbl to gnd to select the 2.5v preset linear regulator output voltage (outl). connect fbl to the center tap of a resistive voltage-divider between outl and gnd to set an adjustable output voltage. in adjustable mode, fbl is regulated at 1.25v nominal. place the resistive divider within 5mm of fbl. 10 outl logic linear regulator output. output of the 2.5v or adjustable linear regulator. bypass to gnd with a 10f (min) capacitor. 11 in supply input. +2.6v to +5.5v input range. supply input for the ic and input for the internal logic linear regulator. bypass to gnd with a 0.1f capacitor within 5mm of the ic pins. 13 gnd analog ground. connect to power ground (pgnd) underneath the ic. 14 ref internal reference output. bypass ref to gnd with a 0.22f (min) capacitor. ref can supply up to 50a to an external load. 15 fbn negative charge-pump feedback input. connect a resistor-divider from the output (outn) to fbn to the reference output (ref). place the resistor-divider within 5mm of fbn. 16, 17 i.c. internally connected. make no connection to this pin. 18 c3p positive terminal of flying capacitor c3 19 supn negative charge-pump supply voltage. bypass to pgnd with a 0.1f capacitor. 21 lx power mosfet n-channel drain and switching node. connect the inductor and catch diode to lx and minimize the trace area for lowest emi. 22 pgnd power ground. pgnd is the source of the main boost/n-channel power mosfet. connect pgnd to the output capacitor ground terminals through a short, wide pc board trace. 24 dlp positive charge-pump startup delay input. connect a capacitor from dlp to gnd to set the delay time. a 5a current source charges c dlp . dlp is pulled to gnd by a 20 ? switch when shut down. 25 shdn active-low shutdown control input. all outputs are disabled when shdn is low. when shdn is high, ref and outl are enabled and the lcd supplies can be enabled if lcdon is high. 26 lcdon lcd supply enable input. all lcd supply outputs (main, outn, and outp) are disabled when lcdon is low. ref and outl are unaffected by lcdon. 27 c1n negative terminal of flying capacitor c1 28 c1p positive terminal of flying capacitor c1
MAX8753 tft lcd dc-dc converter with integrated charge pumps 10 ______________________________________________________________________________________ typical operating circuit the MAX8753 typical application circuit (figure 1) gen- erates a +2.5v logic supply, a +9v source driver sup- ply, and +24v and -11v gate-driver supplies for tft displays. the input voltage range for the ic is from +2.6v to +5.5v. table 1 lists the recommended components and table 2 lists the contact information for component suppliers. in i.c. supp supn shdn lcdon outl fbl dlp intg lx pgnd gnd fb c3p fbn ref outp fbp i.c. 6 1 21 11 16 17 19 25 26 10 9 24 22 13 7 18 n.c. 2 n.c. 12 n.c. 20 n.c. 23 15 14 5 8 v in +2.6v to +5.5v c in 10 f l1 6.8 h c intg 470pf v main c logic 10 f c dlp 0.1 f d2 d1 c main1 10 f r1 174k ? r comp 20k ? r2 28k ? c comp 1nf d3 c3 0.1 f c neg 1 f c ref 0.22 f r3 215k ? r4 19.1k ? c pos 1 f r5 46.4k ? r6 25.5k ? c1n c1p c2n c2p 27 28 3 4 c1 0.1 f c2 0.1 f 0.1 f 0.1 f v main +9v, 140ma v neg -11v, 10ma v pos +24v, 10ma v logic +2.5v, 300ma 0.1 f c4 0.1 f c5 0.1 f MAX8753 figure 1. typical operating circuit designation description c in , c logic 10f, 6.3v x5r ceramic capacitors (0603) tdk c1608x5r0j106m c main 10f 20%, 16v x5r ceramic capacitor (1210) taiyo yuden emk325 bj106kd d1 3a, 30v schottky diode (m-flat) toshiba cms02 d2, d3 200ma, 100v, dual ultra-fast diodes (sot23) fairchild mmbd4148se l1 6.8h, 1.0a inductor sumida cdh38d09hp table 1. critical component list
MAX8753 tft lcd dc-dc converter with integrated charge pumps ______________________________________________________________________________________ 11 detailed description the MAX8753 quadruple-output dc-dc converter pro- vides the regulated voltages required by active-matrix, tft lcds. figure 1 shows the typical operating circuit. it includes a high-power step-up regulator (v main ), two low-power charge pumps (v pos and v neg ), and a low- voltage, 300ma linear regulator (v logic ). the primary boost converter uses an internal n-channel mosfet to provide maximum efficiency and to minimize the num- ber of external components. the output voltage of the main boost converter (v main ) can be set from v in to 13v with external resistors. the positive charge pump regulates a positive output (v pos ) without external switches or diodes. the negative charge pump regu- lates a negative output (v neg ) with external diodes. a proprietary regulation algorithm minimizes output rip- ple, as well as capacitor sizes for both charge pumps. also included in the MAX8753 is a precision 1.25v ref- erence that sources up to 50a, logic shutdown, soft- start, power-up sequencing, and fault detection. figure 2 is the MAX8753 functional diagram. main step-up regulator the main step-up regulator employs a current-mode, fixed-frequency pwm architecture to maximize loop bandwidth and provide fast transient response to pulsed loads and tft lcd panel source driver applica- tions. the high switching frequency (1mhz) allows the use of low-profile inductors and ceramic capacitors to minimize the thickness of lcd panel designs. the inte- grated high-efficiency mosfet and the ic s built-in, digital, soft-start function reduces the number of exter- nal components required while controlling inrush cur- rent. the output voltage can be set from v in to 13v with an external resistive voltage-divider. the regulator controls the output voltage and the power delivered to the output by modulating the duty cycle (d) of the internal power mosfet in each switching cycle. the duty cycle of the mosfet is approximated by: figure 3 shows the block diagram of the step-up regu- lator. a transconductance error amplifier compares the signal at fb to 1.24v and changes the comp output. the voltage at comp determines the current trip point each time the internal mosfet turns on. as the load varies, the transconductance error amplifier sources or sinks current to the comp output accordingly to pro- duce the inductor peak current necessary to service the load. to maintain stability at high duty cycles, a d vv v main in main ? MAX8753 step-up regulator shdn in lx fb dlp gnd seq pgnd ldo fbl outl positive charge- pump regulator negative charge- pump regulator ref fbn ref fbp outp c1n c1p c2n c2p supn supp onlcd intg c3p figure 2. functional diagram supplier phone fax website fairchild 408-822-2000 408-822-2102 www.fairchildsemi.com sumida 847-545-6700 847-545-6720 www.sumida.com taiyo yuden 408-573-4150 408-573-4159 www.t-yuden.com tdk 847-803-6100 847-390-4405 www.component.tdk.com toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec table 2. component suppliers
MAX8753 tft lcd dc-dc converter with integrated charge pumps 12 ______________________________________________________________________________________ slope compensation signal is summed with the current- sense and feedback signals. on the rising edge of the internal clock, the controller sets a flip-flop, turning on the n-channel mosfet and applying the input voltage across the inductor. the cur- rent through the inductor ramps up linearly, storing energy in its magnetic field. once the sum of the cur- rent-feedback signal and the slope compensation exceed the comp voltage, the controller resets the flip- flop, and turns off the mosfet. since the inductor cur- rent is continuous, a transverse potential develops across the inductor (l1) that turns on the diode (d1). the voltage across the inductor then becomes the dif- ference between the output voltage and the input volt- age. this discharge condition forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and the load. the mosfet remains off for the rest of the clock cycle. positive charge-pump regulator the positive charge-pump regulator is typically used to generate the positive supply rail for the tft lcd gate- driver ics (figure 4). the output voltage is set with an external resistive voltage-divider from its output to gnd with the midpoint connected to fbp. the positive charge pump is a voltage tripler that accepts an input voltage up to +13v and delivers a 20ma output up to +28v without external switches or diodes. during the first half-cycle (clk is low), c1n pin is con- nected to the ground, which allows v supp to charge up the first flying capacitor c1 through diode d1. the amount of charge transferred from v supp to c1 is determined by the on-resistance of n1, which varies according to the output of the feedback error amplifier. during the second half-cycle (clk is high), c1n is con- nected to v supp through p1, level shifting c1 by v supp volts. the on-resistance of p1 is also controlled by the output of the feedback error amplifier. meanwhile, clkb becomes low, pulling c2n to the ground. this connects c1 in parallel with the second flying capacitor MAX8753 ref lx dc-dc logic drv pgnd cs csn ref ref osc slope comp osc 1.1v ref-ok csp fb gm buffer ean sc eap in gnd v in = 2.6v to 5.5v l1 d1 v main (up to 13v) r1 r2 r comp c comp c intg intg c ref c main1 ea figure 3. step-up regulator block diagram
MAX8753 tft lcd dc-dc converter with integrated charge pumps ______________________________________________________________________________________ 13 c2. if the voltage across c2 plus a diode drop (v c2 + v diode ) is smaller than the first level-shifted flying capacitor voltage (v c1 + v supp ), charge flows from c1 to c2 until diode d2 turns off. similarly, when clkb becomes high, c2 is also level shifted by v supp volts. this connects c2 in parallel with the reservoir capacitor c pos . if the voltage across c pos plus a diode drop (v pos + v diode ) is smaller than the second level-shift- ed flying capacitor voltage (v c2 + v supp ), charge flows from c2 to c pos until diode d3 turns off. negative charge-pump regulator the negative charge-pump regulator is typically used to generate the negative supply rail for the tft lcd gate-driver ics. the output voltage is set with an exter- nal resistive voltage-divider from its output to ref with the midpoint connected to fbn. the number of charge- pump stages and the setting of the feedback divider determine the output of the negative charge-pump reg- ulator. the charge-pump controller includes a high-side p-channel mosfet (p3) and a low-side n-channel mosfet (n3) to control the power transfer as shown in figure 5. the negative charge pump can also be con- figured as a multiple-stage charge pump. the required number of stages (n neg ) is determined by v supn and the desired negative output voltage. figure 1 gives an example with a two-stage negative charge pump. in figure 5, during the first half-cycle, the p-channel mosfet turns on and flying capacitor c3 charges to v supn minus a diode drop. during the second half- cycle, the p-channel mosfet turns off, and the n-chan- nel mosfet turns on, level shifting c3. this connects c3 in parallel with the reservoir capacitor c neg . if the voltage across c3 minus a diode drop is lower than the voltage across c neg , charge flows from c3 to c neg until the diode turns off. the amount of charge trans- ferred to the output is controlled by the variable n-chan- nel on-resistance. MAX8753 c1p c2p c2n d1 d2 d3 fbp ref ref supp ov threshold r1 r2 c1n outp supp r5 r6 c pos c1 c2 p1 n1 c1n clk r on control p2 n2 c2n r on control clk ctrl ea osc ea v pos v supp charge- pump logic figure 4. positive charge-pump regulator block diagram
MAX8753 tft lcd dc-dc converter with integrated charge pumps 14 ______________________________________________________________________________________ linear regulator the MAX8753 contains a linear regulator that uses an internal pmos transistor to supply load currents up to 300ma. connect fbl to gnd to set the linear regulator output to 2.5v. connect an external resistive voltage- divider between the regulator output and gnd with the midpoint connected to fbl to adjust the linear-regulator output. an error amplifier compares the fbl voltage with the 1.25v internal reference voltage and amplifies the difference. if the feedback voltage is higher than the ref- erence voltage, the controller lowers the gate voltage of the pmos transistor, which reduces the amount of cur- rent delivered to the output. if the feedback voltage is too low, the device increases the pmos transistor s gate voltage, which allows more current to pass to the output and raises the output voltage. the linear regulator also includes an output current limit that protects the internal pass transistor against short circuits. the linear regulator is enabled whenever ref is in reg- ulation and shdn is logic-high. the linear regulator current-limit circuitry monitors the current flowing through the internal pass transistor. the internal current limit is approximately 500ma. the linear regulator output declines when it is not able to supply the load current. if the fbl voltage drops below 0.75v, the current limit folds back to approximately 100ma. reference voltage (ref) the reference output is nominally 1.25v and can source up to 50a. bypass ref with a 0.22f ceramic capacitor connected between ref and gnd. the refer- ence remains disabled in shutdown. power-up sequence and shutdown control when the MAX8753 is powered up, all outputs are dis- abled as long as shdn is low. after shdn is logic- high, the reference and the linear regulator power up first. the main dc-dc step-up converter, the negative p3 n3 d4 c3 c neg c ref r3 r4 v neg 1.25v 250mv gnd pgnd ref fbn c3p supn osc charge- pump logic v supn d5 r on control MAX8753 ea figure 5. negative charge-pump regulator block diagram
MAX8753 tft lcd dc-dc converter with integrated charge pumps ______________________________________________________________________________________ 15 charge pump, and the positive charge pump remain disabled until lcdon is high. when lcdon is logic- high, the main dc-dc step-up converter powers up with soft-start enabled. once the main step-up converter reaches regulation, the negative charge pump turns on. when the main step-up converter reaches regulation, the positive charge-pump regulator delay block is enabled. an internal current source starts charging the dlp capacitor. the voltage on dlp linearly rises because of the constant-charging current. when v dlp goes above v ref , the switch control block is enabled, and the positive charge-pump regulator begins its soft- start. after the positive charge-pump regulator s soft- start is completed, the fault protection of the positive charge-pump regulator is also enabled. a logic-low level on lcdon disables the main boost converter, the negative charge pump, and the positive charge pump. the output capacitance and load current determine the rate at which each output voltage decays. the linear regulator and the reference remain enabled unless shdn drops below its logic-low thresh- old. when shut down, the reference turns off and the ic supply current drops to 0.1a to maximize battery life in portable applications. do not leave shdn floating. if unused, connect shdn to in. output fault protection during steady-state operation if the output of the linear regulator, the step-up regulator, or either of the charge- pump regulator outputs, does not exceed its respective fault-detection threshold, the MAX8753 activates an internal fault timer. if any condition or combination of conditions indicates a continuous fault for the fault timer duration (50ms typ), the MAX8753 sets the fault latch, shutting down all the outputs except the reference. once the fault condition is removed, cycle the input voltage or toggle shdn to clear the fault latch and reactivate the device. each regulator s fault-detection circuit is dis- abled during the regulator s soft-start time. thermal-overload protection the thermal-overload protection prevents excessive power dissipation from overheating the ic. if the junc- tion temperature exceeds +160 c, a thermal sensor immediately activates the thermal fault protection, which shuts down all the outputs, allowing the device to cool down. once the device cools down, cycle the input voltage to clear the thermal fault latch and reacti- vate the device. design procedure main step-up regulator inductor selection the minimum inductance value, peak current rating, and series resistance are factors to consider when selecting the inductor. these factors influence the converter s effi- ciency, maximum output load capability, transient response time, and output voltage ripple. physical size and cost are also important factors to be considered. the maximum output current, input voltage, output volt- age, and switching frequency determine the inductor value. very high inductance values minimize the cur- rent ripple and therefore reduce the peak current, which decreases core losses in the inductor and i 2 r losses in the entire power path. however, large induc- tor values also require more energy storage and more turns of wire, which increase physical size and can increase i 2 r losses in the inductor. low inductance val- ues decrease the physical size but increase the current ripple and peak current. finding the best inductor involves choosing the best compromise between circuit efficiency, inductor size, and cost. the equations used here include a constant lir, which is the ratio of the inductor peak-to-peak ripple current to the average dc inductor current at the full-load cur- rent. the best trade-off between inductor size and cir- cuit efficiency for step-up regulators generally has an lir between 0.3 and 0.5. however, depending on the ac characteristics of the inductor core material and ratio of inductor resistance to other power-path resis- tances, the best lir can shift up or down. if the induc- tor resistance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. if the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. if extremely thin high-resistance inductors are used, as is common for lcd panel applications, the best lir can increase to between 0.5 and 1.0. once a physical inductor is chosen, higher and lower values of the inductor should be evaluated for efficien- cy improvements in typical operating regions. in figure 1 s typical operating circuit, the lcd s gate- on and gate-off voltages are generated from two charge pumps powered by the step-up regulator. the additional load on v main must therefore be considered in the inductance calculation. the effective maximum output current i main(eff) becomes the sum of the maxi- mum load current on the step-up regulator s output
MAX8753 tft lcd dc-dc converter with integrated charge pumps 16 ______________________________________________________________________________________ plus the contributions from the positive and negative charge pumps: where i main(max) is the maximum output current, n neg is the number of negative charge-pump stages, i neg is the negative charge-pump output current, and i pos is the positive charge-pump output current. calculate the approximate inductor value using the typ- ical input voltage (v in ), the maximum output current (i main(max) ), the expected efficiency ( typ ) taken from an appropriate curve in the typical operating characteristics , and an estimate of lir based on the above discussion: choose an available inductor value from an appropriate inductor family. calculate the maximum dc input cur- rent at the minimum input voltage v in(min) using con- servation of energy and the expected efficiency at that operating point ( min ) taken from an appropriate curve in the typical operating characteristics : calculate the ripple current at that operating point and the peak current required for the inductor: the inductor s saturation current rating and the MAX8753 s lx current limit (i lx(max) ) should exceed i peak and the inductor s dc current rating should exceed i in(dc,max) . for good efficiency, choose an inductor with less than 0.1 ? series resistance. considering the typical operating circuit, the maximum load current (i main(max) ) is 140ma with a 9v output and a typical input voltage of 3.3v: choosing an lir of 0.45 and estimating efficiency of 80% at this operating point: using the circuit s minimum input voltage (2.6v) and estimating efficiency of 70% at that operating point: the ripple current and the peak current are: output capacitor selection the total output-voltage ripple has two components: the capacitive ripple caused by the charging and discharg- ing of the output capacitance, and the ohmic ripple due to the capacitor s equivalent series resistance (esr): where i peak is the peak inductor current (see the inductor selection section). for ceramic capacitors, the output voltage ripple is typically dominated by v ripple(c) . the voltage rating and temperature charac- teristics of the output capacitor must also be considered. input capacitor selection the input capacitor (c in ) (see figure 1) reduces the current peaks drawn from the input supply and reduces noise injection into the ic. a 10f ceramic capacitor is used in the typical operating circuit (figure 1) because of the high source impedance seen in typical lab setups. actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated sup- ply. typically, c in can be reduced below the values used in the typical operating circuit. ensure a low noise supply at in by using adequate c in . vir ripple esr peak esr cout () ( ) v i c vv vf and ripple c main out main in main osc () ? ? ? ? ? ? ? vv v ripple ripple c ripple esr =+ () ( ) ia a a peak =+ = 094 027 2 108 . . . i vv v h v mhz a ripple = ? () = 26 9 26 68 9 1 027 .. . . i av v a in dc max (, ) . .. . = 019 9 26 07 094 l v v vv a mhz h = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 33 9 933 019 1 080 045 68 2 .. . . . . imamamama main eff () = ++= 140 2 10 3 10 190 ii i peak in dcmax ripple =+ (, ) 2 i vvv lv f ripple in min main in min main osc = ? () () () i iv v in dcmax main eff main in min min (, ) () () = l v v vv iflir in main main in main eff osc typ = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 () ii nii main eff main max neg neg pos () ( ) =++ 3
MAX8753 tft lcd dc-dc converter with integrated charge pumps ______________________________________________________________________________________ 17 rectifier diode the MAX8753 s high switching frequency demands a high-speed rectifier. schottky diodes are recommend- ed for most applications because of their fast recovery time and low forward voltage. in general, a 2a schottky diode complements the internal mosfet well. output-voltage selection the output voltage of the main step-up regulator can be adjusted by connecting a resistive voltage-divider from the output (v main ) to gnd with the center tap connected to fb (see figure 1). select r2 in the 10k ? to 50k ? range. calculate r1 with the following equation: where v fb , the step-up regulator s feedback set point, is 1.245v. place r1 and r2 close to the ic. loop compensation for stability, add a pole-zero pair from fb to gnd in the form of a series resistor (r comp ) and capacitor (c comp ). r comp should be approximately half the value of the r2 feedback resistor. to further optimize transient response, vary r comp in 20% steps and c comp in 50% steps while observing transient response waveforms. charge-pump regulators output voltage selection adjust the positive charge-pump regulator output volt- age by connecting a resistive voltage-divider from the regulator output v pos to gnd with the center tap con- nected to fbp (figure 1). select the lower resistor of the divider r6 in the 10k ? to 50k ? range. calculate upper resistor r5 with the following equation: where v fbp = 1.25v (typ) is the regulation point of the positive charge-pump regulator. adjust the negative charge-pump regulator output volt- age by connecting a resistive voltage-divider from the negative charge-pump output v neg to ref with the center tap connected to fbn (figure 1). select r4 in the 20k ? to 100k ? range. calculate r3 with the follow- ing equation: where v ref = 1.25v, and v fbn = 250mv is the regula- tion point of the negative charge-pump regulator. flying capacitor increasing the flying capacitor (c x ) value lowers the effective source impedance and increases the output- current capability of the charge pump. increasing the capacitance indefinitely has a negligible effect on out- put-current capability because the internal switch resis- tance and the diode impedance place a lower limit on the source impedance. a 0.1f ceramic capacitor works well in most low-current applications. the flying capacitor s voltage rating must exceed the following: charge-pump input capacitor use an input capacitor on supp and supn with a value equal to or greater than the flying capacitors on that charge pump. place the capacitors as close to supp and supn as possible. connect the capacitors directly to pgnd. charge-pump output capacitor increasing the output capacitance or decreasing the esr reduces the output ripple voltage and the peak-to- peak transient voltage. with ceramic capacitors, the output-voltage ripple is dominated by the capacitance value. use the following equation to approximate the required capacitor value: where c out_cp is the output capacitor of the charge pump, i load_cp is the load current of the charge pump, and v ripple_cp is the desired peak-to-peak value of the output ripple. charge-pump rectifier diode use low-cost silicon switching diodes for d2 and d3 with a current rating equal to or greater than two times the average charge-pump input current. if it helps avoid an extra stage, some or all of the diodes can be replaced with schottky diodes with an equivalent cur- rent rating. c i fv out cp load cp osc ripple cp _ _ _ 2 vv vv vv v v if used c supp c supp c supn c supn 1 2 3 4 2 2 > > > > , rr vv vv fbn neg ref fbn 34 = ? ? rr v v pos fbp 56 1 = ? ? ? ? ? ? ? rr v v main fb 12 1 = ? ? ? ? ? ? ?
MAX8753 tft lcd dc-dc converter with integrated charge pumps 18 ______________________________________________________________________________________ applications information power dissipation an ic s maximum power dissipation depends on the thermal resistance from the die to the ambient environ- ment and the ambient temperature. the thermal resis- tance depends on the ic package, pc board copper area, other thermal mass, and airflow. the MAX8753, with its exposed backside paddle sol- dered to 1in 2 of pc board copper, can dissipate about 1.7w into +70 c still air. more pc board copper, cooler ambient air, and more airflow increase the possible dissi- pation while less copper or warmer air decreases the ic s dissipation capability. the major components of power dissipation are the power dissipated in the step- up regulator, the linear regulator, and the charge pumps. step-up regulator the largest portions of power dissipation in the step-up regulator are the internal mosfet, inductor, and the output diode. if the step-up regulator has 90% efficien- cy, approximately 3% to 5% of the power is lost in the internal mosfet, approximately 3% to 4% in the induc- tor, and approximately 1% in the output diode. the remaining 1% to 3% is distributed among the input and output capacitors and the pc board traces. if the input power is approximately 5w, the power lost in the inter- nal mosfet is approximately 150mw to 250mw. linear regulator the power dissipation in the linear regulator is: positive charge-pump regulator the power dissipation in the positive charge-pump reg- ulator is: negative charge-pump regulator the power dissipation in the negative charge-pump regulator is: pc board layout and grounding careful pc board layout is important for proper opera- tion. use the following guidelines for good pc board layout: 1) minimize the area of the step-up regulator s high- current loops by placing the inductor (l1), output diode (d1), and output capacitor (c main ) near the input capacitor (c in ) and near the lx and pgnd pins. the high-current input loop goes from the posi- tive terminal of c in to l 1 , to the ic s lx pin, out of pgnd, and to c in s negative terminal. the high-cur- rent output loop is from the positive terminal of c in to l1, to the output diode (d1), to the positive termi- nal of c main , reconnecting between the output capacitor and input capacitor ground terminals. connect these loop components with short, wide connections. avoid using vias in the high-current paths. if vias are unavoidable, use many vias in par- allel to reduce resistance and inductance. 2) create a power-ground island (pgnd) consisting of the input and output capacitor grounds, pgnd pin, the charge-pump input capacitors, output capaci- tors, and diodes. connect these together with short, wide traces or a small ground plane. maximizing the width of the power-ground traces improves efficien- cy and reduces output-voltage ripple and noise spikes. create an analog-ground plane (agnd) consisting of the gnd pin, all the feedback-divider ground connections, the intg and del capacitor ground connections, and the device s exposed backside pad. connect the agnd and pgnd islands by connecting the pgnd pin directly to the exposed backside pad. make no other connections between these separate ground planes. 3) place the feedback voltage-divider resistors as close to the feedback pin as possible. the divider s center trace should be kept short. placing the resistors far away causes the fb traces to become antennas that can pick up switching noise. care should be taken to avoid running any feedback trace near lx or the switching nodes in the charge pumps. 4) place the in and outl bypass capacitors as close to the device as possible. the ground connections of the in and outl bypass capacitors should be connected directly to the pgnd plane near the pgnd pin with a wide trace. pnxvvi d neg neg supn neg neg () () =+ pvvi d pos main pos pos () () = ? 3 pvvi d logic in logic logic () () =?
MAX8753 tft lcd dc-dc converter with integrated charge pumps ______________________________________________________________________________________ 19 5) minimize the length and maximize the width of the traces between the output capacitors and the load for best transient response. 6) minimize the size of the lx node while keeping it wide and short. keep the lx node away from the feedback node and analog ground. use dc traces as shield if necessary. refer to the MAX8753 evaluation kit for an example of proper board layout. chip information transistor count: 6922 process: bicmos
MAX8753 tft lcd dc-dc converter with integrated charge pumps maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. boblet package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45? d/2 d2/2 l c l c e e l c c l k l l detail b l l1 e aaaaa marking i 1 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- l e/2 common dimensions max. exposed pad variations d2 nom. min. min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3 3.20 3.00 3.10 no no no no yes yes yes yes 3.20 3.00 t1655-3 3.10 3.00 3.10 3.20 no no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 yes 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 no 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 yes 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table ?0.15 11. marking is for package orientation reference only. i 2 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only. 3.30 t4055-1 3.20 3.40 3.20 3.30 3.40 ** yes 0.05 00.02 0.60 0.40 0.50 10 ----- 0.30 40 10 0.40 0.50 5.10 4.90 5.00 0.25 0.35 0.45 0.40 bsc. 0.15 4.90 0.25 0.20 5.00 5.10 0.20 ref. 0.70 min. 0.75 0.80 nom. 40l 5x5 max. 13. lead centerlines to be at true position as defined by basic dimension "e", ?0.05. t1655-2 ** yes 3.20 3.10 3.00 3.10 3.00 3.20 t3255-5 yes 3.00 3.10 3.00 3.20 3.20 3.10 ** exceptions

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